1. Field of the Invention
The present invention relates to a digital-to-analog converting circuit and a digital-to-analog converting method which execute digital-to-analog converting by using redundant digital-to-analog converting elements.
2. Description of the Related Art
Generally, an output waveform of a digital-to-analog converting circuit or converter (abbreviated as DAC) includes a Return to Zero (RTZ) waveform and a Non-Return to Zero (NRTZ) waveform. FIG. 11 illustrates ideal waveforms of RTZ and NRTZ in a 1-bit DAC. An output waveform of a DAC is integrated by an integrator and is outputted, which is used for a general continuous time delta/sigma analog/digital converting circuit or converter (abbreviated as ADC), etc.
As illustrated in FIG. 12, because characteristics of the rising and the falling of an output waveform (before being integrated by an integrator) of an actual DAC are different from each other, particularly in a DAC of a NRTZ output, an error of an integrated value is induced depending on an input code (or output code).
As illustrated in a NRTZ example of FIG. 12, if it is assumed that an error attributed to the difference of the rising and the falling is Δ, in the case that an input code is HHHLLHL, an error of the output code is three Δ as understood from the number of parts illustrated by diagonal lines, and in the case that an input code is HLHLHLH, the error is six Δ.
Thus, in the case of NRTZ, when an input code continues and discontinues, an output value of an error attributed to the difference of the rising and the falling (the number of the rising and the falling) is different, so that the integrated value is also different.
A DAC of a RTZ output transitions from a zero status every time, so that an error component does not depend on an input code (it becomes a gain error).
On the other hand, when a DAC output is integrated, a clock jitter (hereinafter, jitter) of a clock which is a synchronizing signal for executing a D/A converting becomes also an error cause. An integrator integrates a DAC output during a clock cycle. As illustrated in FIG. 13, when the same jitter (σ[psec]) is provided to DACs of RTZ and NRTZ output, an amplitude of the RTZ output is 1/δ (δ<1) times as large as an amplitude of the NRTZ output, and the RTZ output is influenced by a jitter every time a clock is inputted, so that it is easily influenced by a jitter. As a bandwidth is wider, the influence of a jitter is more serious.
In a DAC of multiple bits, an error of a conversion level attributed to the production variation of D/A converting elements is also a cause which degrades a linearity of a DAC.
As an improvement measure, it is widely known in the field of the Invention that the linearity is improved by using a matching technology of dynamic elements (dynamic element matching, abbreviated as DEM) as described in the first and second patent documents, U.S. Pat. Nos. 3,982,172 and 4,703,310.
Such a technology has a noise shaping function for performing an operation which prevents the same converting element from being selected in each D/A converting, averages errors, and banishes noises due to the higher harmonic distortion attributed to the variation of D/A converting elements outside the band.
Conventionally, in a configuration of a continuous time delta/sigma ADC, etc., a DAC of RTZ output has been frequently used to reduce the above influence of errors depending on an output waveform.
However, as described above, a RTZ waveform is easily influenced by jitters, so that the influence seriously degrades the accuracy in a wide band usage.
While the above first and second patent documents can reduce errors due to the variation of D/A converting elements with a DEM processing, it can not reduce errors attributed to the difference of the rising and the falling of an output waveform.